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DDR PHY Firmware Engineer

Intel -
Guadalajara, Jal.

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Información del empleo

Tiempo completo
Hace 13 días

Cualificaciones

C#
Firmware
UNIX
Inglés
Maestría
C++
Licenciatura
Linux
Recursos humanos
Liderazgo
Python
Debugging

Descripción completa del empleo

Job Details:

Job Description:

Intel's Central Engineering Group is seeking a DDR/LPDDR Memory Subsystem Firmware Developer to design, develop, and validate DDR and LPDDR memory reference code for our next-generation products working at the critical hardware-software boundary, writing foundational initialization and training algorithms to ensure maximum bandwidth, strict power efficiency, and optimal signal integrity. In this role, you will drive solutions that seamlessly incorporate Intel's cutting-edge products and technologies, playing a pivotal role in enabling ecosystem and industry partners for platform readiness.

You will have the opportunity to design, develop, and validate innovative solutions that shape the future of technology. By collaborating with internal and external teams, you will ensure Intel's products are market-ready and deliver exceptional performance, creating meaningful impact across industries.

This role provides a unique opportunity to influence design, optimize customer experiences, and support the delivery of products that define Intel's success in a rapidly evolving market.

Responsibilities will include but are not limited to:

DDR/LPDDR Reference Code Development: write, maintain, support, optimize and debug low-level firmware in C and C++ for memory initialization, configuration, and runtime management.
Implement and support advanced DRAM training algorithms (e.g., write/read leveling, VREF training) adhering to JEDEC specifications
Execute and test firmware on architectural models, test chip platforms, simulation platforms (FPGA/emulation), and RTL environments before physical silicon is available.
Participate directly in post-silicon bring-up in the lab, diagnosing and resolving complex hardware/firmware integration bugs.
Partner with SoC architecture, analog design, and validation teams to ensure hardware features map correctly to software controls.
Works closely with both the DDR/LPDDR PHY IP Design Team as well as the post silicon Electrical and Functional Validation teams.
Document Memory Reference Code specifications and user guides for OEMs and internal platform engineering teams.
Hands-on automation script development and optimization (using C/C++, Python). Well versed in the usage of advanced lab equipment.
Publishes MRC validation plan and reports summarizing all validation activities performed, reviews results, and communicates to relevant teams.
Collaborate with internal and external silicon, hardware, and software teams to deliver innovative market-ready solutions.
Partner with customers' R and D and manufacturing teams to address factory challenges, integrate DFx requirements, and ensure smooth product ramp.
Deliver product training and provide technical support to drive systematic improvements.
Works validation engineers (e.g., platform, SoC, and sys debug) to understand bug escapes, debug MRC/IP related failures found in other environments
Troubleshoot and resolve technical issues during development, testing, and production phases.
Great team player, highly motivated to support the team with technical expertise and hands on experience in memory reference development and debug.
Knowledge of High-Speed Oscilloscopes, Logic Analyzers, Data Acquisition Tools/Hardware.
Collaborate with internal and external silicon, hardware, and software teams to deliver innovative market-ready solutions.
Partner with customers' R and D and manufacturing teams to address factory challenges, integrate DFx requirements, and ensure smooth product ramp.
Deliver product training and provide technical support to drive systematic improvements.

The ideal candidate should show the following behavioral traits:

Excellent communication and leadership skills.
Proven analytical and problem-solving skills.

Qualifications:

Minimum qualifications are required to be initially considered for this position.

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
5+ years of total experience including experience in the following areas:
- Working/developing/executing test plans. Developing in a Linux/UNIX environment.
- Object-oriented programming in coding any of the languages: C, C++, C# and/or Python Software.

Advanced English level.

Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Experience with memory reference code development and debugging issues related to DDR/LPDDR memory interfaces.
Understanding of the JEDEC Standards for DDR and LPDDR: Desktop/Server, Embedded Hardware, Firmware, system bring-up, and/or silicon Power-On experience.
5+ years of experience with one or more of the following: Hardware and Firmware.
Validation test plans and Firmware test cases development and debug experience.
Proficiency with memory reference code development and debugging issues related to DDR/LPDDR memory interfaces.
Proficiency with system level validation, debugging MRC issues.
Developing test automation experience. Debugging on emulation models.

Job Type:

Experienced Hire

Shift:

Shift 1 (Mexico)

Primary Location:

Mexico, Guadalajara

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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