4 publicaciones de empleo destacadas de low power design en tijuana, bcn (¡Están contratando!)

ASIC DRAM circuit design
NAPS Mexico —Tijuana, B.C.
- $1,000 a $1,001 por día
- Tiempo completo
- Doctorado
- Informática
- Análisis de datos
Postulación rápida
Sr Tooling Engineer
Resideo —Tijuana, B.C.
- Tiempo completo
- Inglés
- Disponible para viajar
- HVAC
Memory Yield Engineer
NAPS Mexico —Tijuana, B.C.
- $1,000 a $1,001 por día
- Tiempo completo
- Doctorado
- Análisis de datos
- Maestría
Postulación rápida
ASIC DRAM Bus and PDN Designer
NAPS Mexico —Tijuana, B.C.
- $1,000 a $1,001 por día
- Tiempo completo
- Doctorado
- Análisis de datos
- Maestría
Postulación rápida

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Sr Tooling Engineer
Resideo —Tijuana, B.C.
Interact with cross functional teams to achieve tooling milestones such as, scheduled tool refurbishings, and urgent tool repairs.
Sr Process Engineer
Medtronic —Tijuana, B.C.
This can include scouting and feasibility work, material selection, process and equipment selection, tooling / fixture and equipment installation and assessment…
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ASIC DRAM circuit design

NAPS Mexico
Tijuana, B.C.

Postulación rápida

Información del empleo

Tiempo completo
$1,000 a $1,001 por día

Cualificaciones

Doctorado
Informática
Análisis de datos
Maestría
Licenciatura
Python

Descripción completa del empleo

We are seeking a highly skilled engineer to develop 2.5D/3D chiplet and networking solution based on technology-systems co-optimized for a unique era of heterogeneous compute as Moore’s law slows down. The candidate is expected to be an expert in recent technology-architecture trends for heterogeneous low power high performance compute and AI compute. He/she should be able to apply that knowledge to influence the company's’s next generation SoC and platform architectures, including partitions for logic and Cache, DRAM memories, and involving 2.5D/3D chiplets and networking technologies to connect them. Knowledge of emerging optical networking technology is a plus.

Candidate will also drive innovation in the group and across the company's’s product BUs to effectively map emerging AI and other compute use cases to process and chip-integration solutions with detailed knowledge of process technology, 2.5D/3D chiplet architecture, networking technologies, and trade-offs. Knowledge of different IPs (e.g., CPU, GPU, NPU) and how they act together to drive an E2E use case is a plus. Candidate will work with internal architecture and system teams to develop 2.5D/3D partitions and map to 3D stacking topologies. Candidate will perform system KPI analysis to drive 3D architecture and stacking strategies for new product introduction.

Minimum Qualifications:

Experience with 2.5D and 3D STCO and pathfinding.
Excellent understanding of generic and AI use case KPI dependency on process and system architecture involving 2.5D/3D chiplets and networking technologies.
Good knowledge of heterogeneous architecture, 2.5D/3D integration schemes.
Basic programming skills e.g., ability to model (e.g., in Python or other languages), system use case impact of 3D architectures, and integration schemes.
Master's or PhD in Electrical Engineering, Computer Science, or a related field.
Ability to work across teams and BUs.
Ability to work without supervision and as part of a team.
Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach.
Advanced data analysis and interpretation skills are required.

Education:

Bachelor’s degree in science, Engineering, or related field and 5+ years of relevant heterogeneous System and technology or related work experience.
OR Master's degree in Science, Engineering, or related field and 4+ years of heterogeneous System and technology or related work experience.
OR PhD in Science, Engineering, or related field and 3+ years of heterogeneous System and technology or related work experience.

Job Type: Full-time

Pay: $1,000.00 - $1,001.00 per day

Work Location: In person

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low power design empleos en tijuana, bcn

ASIC DRAM circuit design

Sr Tooling Engineer

Memory Yield Engineer

ASIC DRAM Bus and PDN Designer

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