3 publicaciones de empleo destacadas de memory mask layout en baja california (¡Están contratando!)

Memory Mask Layout Design Engineer
North American Production Sharing —Tijuana, B.C.
- Informática
- CAD
- Experiencia en bases de datos
Postulación rápida
Memory -Mask Layout Designer
NAPS Mexico —Tijuana, B.C.
- $1,000 a $1,001 por día
- Tiempo completo
- Informática
- CAD
- Experiencia en bases de datos
Postulación rápida
Memory Mask Layout Designer
Qualcomm —Tijuana, B.C.
- Informática
- CAD
- Experiencia en bases de datos

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Standard Cell Layout Engineer
Qualcomm —Tijuana, B.C.
Maintain and manage layout databases using designated Design Management software. Collaborate closely with circuit designers to ensure layouts meet quality,…
Memory -Mask Layout Designer
NAPS Mexico —Tijuana, B.C.
Maintain layout database utilizing Design Management software. Familiarity with scripting languages (SKILL, Python) for layout automation.
$1,000 a $1,001 por día
Postulación rápida

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Memory Mask Layout Design Engineer

North American Production Sharing -
Tijuana, B.C.

Postulación rápida

Información del empleo

Cualificaciones

Informática
CAD
Matemáticas
Experiencia en bases de datos
Licenciatura
Python

Descripción completa del empleo

Job Summary:

We are looking for a highly motivated SRAM Mask Layout Designer to join our custom memory design team. This entry-level position offers an opportunity to work on cutting-edge semiconductor technologies and gain hands-on experience in physical layout design for SRAM and other memory circuits.

Job description:

Assist in creating physical layouts for SRAM and custom memory blocks using industry-standard CAD tools (e.g., Cadence Virtuoso).
Perform layout verification including DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC.
Collaborate with circuit designers to ensure layout meets performance, reliability, and manufacturability requirements.
Maintain layout database utilizing Design Management software.
Engage with the engineering design team to understand design concepts, constraints, and milestones. Concisely and accurately report design status to the layout and engineering team; track schedules.
Proactively and independently solve design and PDK issues; clearly communicate solutions to the layout and engineering team.
Work closely with circuit Designers/ Mask Layout Designers across global sites (such as the U.S., Taiwan and India)
Demonstrate effective communication and teamwork; work efficiently as part of an international team.

Minimum Qualifications:

Associate’s degree/Certificate in computer Science, Mathematics, Electrical Engineering or related field
Basic understanding of CMOS technology and IC design principles.
Strong attention to detail and ability to work in a team environment.

Preferred Qualifications:

Bachelor’s degree in computer science, Engineering, or related field.
Understanding of parasitic effects and reliability considerations.
Familiarity with scripting languages (SKILL, Python) for layout automation.
Knowledge of advanced process nodes (e.g., FinFET, GAA) is a plus.

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Memory Mask Layout Design Engineer

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