6 publicaciones de empleo destacadas de technical support en tijuana, bcn (¡Están contratando!)

SoC Design & Synthesis Engineer
North American Production Sharing —Tijuana, B.C.
- Doctorado
- Maestría
- Licenciatura
Postulación rápida
7d
Técnico de Mantenimiento (Maintenance Technician)
MARKWINS BEAUTY BRANDS INC —Tijuana, B.C.
- Tiempo completo
- Experiencia en almacén
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Campaign & Content Operations Specialist
ScaleUp —Tijuana, B.C.
- $1,500 a $2,000 por mes
- Tiempo completo
Postulación rápida
MAINTENANCE MECHANIC V
TE Connectivity —Tijuana, B.C.
- Bachillerato
- Disponible para viajar
- Experiencia en manufactura
7d
PHARMACEUTICAL – SR. C&Q ENGINEER
MMR Consulting —Tijuana, B.C.
- Disponible para viajar
- Limpieza
- Liderazgo
Postulación rápida
Senior Social Media Specialist
Legal Management Group —Tijuana, B.C.
- Tiempo completo
- Mercadotecnia
- Inglés
- Licenciatura
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Técnico de Mantenimiento (Maintenance Technician)
MARKWINS BEAUTY BRANDS INC —Tijuana, B.C.
They also carry out regular maintenance checks. También llevan a cabo revisiones periódicas de mantenimiento. Carrera técnica o carrera trunca (Deseable).
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SoC Design & Synthesis Engineer

North American Production Sharing -
Tijuana, B.C.

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Información del empleo

Hace 7 días

Cualificaciones

Doctorado
Maestría
Licenciatura
Debugging

Descripción completa del empleo

SoC Design & Synthesis Engineer

This role focuses on synthesizing large‑scale SoC RTL designs into high‑quality gate‑level netlists that are ready for Place & Route. Responsibilities include owning all synthesis inputs, executing multi‑stage synthesis flows, and ensuring netlist quality with respect to timing, power, and DFT requirements prior to Physical Design handoff.

The role also contributes to PPA (Power, Performance, Area) optimization by analyzing trade‑offs and recommending design or constraint improvements, while working closely with Design, DFT, and Physical Design teams to resolve issues early in the flow. In addition, the engineer supports functional ECOs and validates post‑change correctness to improve functionality and fix late‑stage issues, ensuring timely delivery of robust, manufacturable designs used in Snapdragon products across mobile, automotive, and edge AI platforms.

Required Skills

Strong understanding of RTL‑to‑gate synthesis for large SoC designs
Experience with gate‑level netlist quality checks and PD‑ready handoffs
Solid knowledge of timing constraints (SDC) across functional and test modes
Ability to analyze and optimize PPA (Power, Performance, Area) trade‑offs
Experience supporting or implementing functional ECOs and validating correctness
Effective debugging, analytical thinking, and execution under tight project schedules

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. or
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. or
PhD in Science, Engineering, or related field.

Preferred Qualifications:

Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.

3+ years of ASIC design, verification, validation, integration, or related work experience.
2+ years of experience with architecture and design tools.
2+ years of experience with scripting tools and programming languages.

2+ years of experience with design verification methods.

Principal Duties & Responsibilities:

Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.

Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.

Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.

Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.

Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.

Writes detailed technical documentation for EDA/IP/ASIC projects.

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