This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.
As a Layout Design Intern, you will be part of a high impact engineering team contributing to the development of next generation semiconductors. In this role, you will support layout implementation of custom IP blocks and APR partitions.
You will work on assignments that are complex, nonstandard, and require strong technical judgment within broadly defined design parameters.
Responsibilities will include but are not limited to:
- Execute physical layout design tasks while ensuring adherence to best in class design practices and efficiency standards.
- Independently assess, plan, and drive complex layout design assignments from definition through completion.
- Collaborate with senior engineers to develop layout methodologies, automation scripts, and custom macros (experience or interest in scripting is a plus).
The ideal candidate must show the following behavioral traits:
- Eagerness to learn and apply new technical concepts.
- Proactive, ownership and accountability for assigned tasks.
- Willing to work effectively in a team-oriented environment.
- Organized, focused on managing multiple tasks.
- Open to feedback and continuous improvement.
What you will learn:
- Advanced VLSI layout methodologies used in modern CPU development.
- Physical implementation flows, including floor planning, routing, design rule checks (DRC), and layout vs. schematic verification (LVS).
- EDA tools and automation, learning how to optimize layout productivity and quality through scripting and custom methodologies.
Microprocessor architecture fundamentals and how physical design impacts power, performance, and area (PPA).
- Cross-functional engineering collaboration, working directly with design, architecture, and verification teams.
- This internship provides exposure to real product development cycles and prepares students for full time roles in physical design, CPU design, or custom circuit layout.
Minimum Qualifications are required to be initially considered for this position.
- Pursuing a Bachelor's or Master degree in Electrical Engineering, Electronic Engineering or Mechatronics Engineering (1 year remaining as an active student).
- Advance English level.
Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).
Preferred Qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- 3+ months Coursework, Internship, and/or experience in any of the following areas:
- Familiarity with VLSI and CMOS logic circuit design.
- Knowledge of Unix/Linux operating systems.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
A candidate who accepts an offer of employment in Mexico is required to present their own personal identification information and numbers for the following: Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number.
Student / Intern
Shift 1 (Mexico)
Mexico, Guadalajara
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
