<h1><b>Job Details:</b></h1><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Job Description: </h2><p>This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.</p><p></p><p>The IOTS Pathfinding team is seeking a motivated and detail-oriented Engineer Intern to join our team in Guadalajara. In this role, you will support readiness and scalability for next-generation high-speed I/O technologies (PCI Express, UPI, CXL, USB) by assisting in technology pathfinding projects critical to future server platforms and Intel's data center leadership. You will develop and validate high-fidelity 3D electromagnetic (EM) model libraries for key interconnects-such as connectors, PCB vias, and high-speed cables-using industry-standard tools (e.g., Ansys HFSS, CST, ADS) to support signal integrity (SI) and power integrity (PI) evaluations.</p><p></p><p>You will collaborate with engineers across Intel's I/O community and, as needed, interact with external industry organizations. Under mentorship, you will help execute parametric studies and optimization sweeps to explore SI/PI performance and manufacturability tradeoffs, assist with correlating simulations to lab/bench measurements, and contribute to documentation such as a best-practices / design-guidelines report and reusable modeling workflows for design teams.</p><p></p><p><b>Key Responsibilities </b></p><ul><li><span>Assist in building, parameterizing, and organizing 3D EM models for connectors, PCB via structures, and high-speed cable/interconnect assemblies using tools such as Ansys HFSS, CST Microwave Studio, and/or ADS. </span></li><li><span>Run defined parametric studies (geometry, materials, plating/roughness, stack-up, launch transitions) to quantify impact on SI/PI metrics (e.g., insertion/return loss, impedance, mode conversion, crosstalk, resonance behavior) and summarize results. </span></li><li><span>Support model validation and correlation by helping compare EM results to lab/bench data (e.g., VNA measurements, TDR, fixture de-embedding) and documenting model assumptions, accuracy, and limitations. </span></li><li><span>Assist with analysis of simulation results to identify trends and potential optimization opportunities, and help capture design tradeoffs (performance, cost, manufacturability) for connector/via/cable implementations. </span></li><li><span>Help create and maintain deliverables including model files/libraries, solver setups, scripts for parameter sweeps and post-processing, and clear documentation to enable reuse by design teams. </span></li><li><span>Contribute to a best-practices report and modeling/optimization guidelines for EM extraction workflows supporting SI/PI assessment of connectors, vias, and high-speed cables (e.g., recommended steps, settings, and checklists). </span></li><li><span>Present progress and findings in team meetings; collaborate with SI/PI, package/board design, and validation engineers to incorporate feedback and improve the model library and documentation. </span></li></ul><p></p><p><b>Behavioral Traits </b></p><ul><li><span>Eagerness to learn and apply new technical concepts. </span></li><li><span>Sense of ownership and accountability for assigned tasks. </span></li><li><span>Work effectively in a team-oriented environment. </span></li><li><span>Proactive, organized, and able to manage multiple tasks. </span></li><li><span>Open to feedback and continuous improvement. </span></li></ul><p></p><p><b>What You Will Learn </b></p><ul><li><span>Experience with 3D electromagnetic (EM) simulation for interconnects using industry tools such as Ansys HFSS, CST Microwave Studio, and/or ADS. </span></li><li><span>Skills on signal integrity (SI) and power integrity (PI) behavior of connectors, PCB vias, and high-speed cables using frequency/time-domain metrics (e.g., S-parameters, TDR, crosstalk). </span></li><li><span>Skills in workflow automation for parametric sweeps and post-processing (e.g., scripting, data reduction, plotting) to turn simulation runs into actionable insights. </span></li><li><span>Exposure to model validation and correlation methods, including comparing simulations to lab/bench measurements (e.g., VNA, TDR) and understanding fixture effects and de-embedding concepts. </span></li><li><span>Experience in creating reusable model libraries and best-practices guidelines, and how to communicate technical results effectively across SI/PI, board design, and validation teams.</span></li></ul><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2><b>Qualifications:</b></h2><p>Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.</p><p>Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.</p><p></p><p><b>Minimum Qualifications:</b></p><ul><li><span>Pursuing a Bachelor', Master's degree or PhD's Degreen in Electronics</span><span> or Electrical Engineering, Computer Engineering, Mechatronics, or a related technical field (with at least 1 year remaining before graduation). </span></li><li><span><span> </span>3+ months of experience in Electrical Engineering (both Digital and Analog Electronics). </span></li><li><span>Advance English level. </span></li><li><span>Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship). </span></li></ul><p></p><p><b>Preferred Qualifications:</b></p><ul><li><span>Familiarity with signal integrity (SI) fundamentals for high-speed links (e.g., insertion/return loss, impedance discontinuities, crosstalk, mode conversion). </span></li><li><span>Exposure to power integrity (PI) concepts (e.g., PDN impedance, decoupling, resonance, target impedance). </span></li><li><span>Hands-on or academic experience with EM simulation tools (Ansys HFSS, CST Microwave Studio, Keysight ADS, or similar). </span></li><li><span>Understanding S-parameters and basic RF/microwave measurements; familiarity with VNA and/or TDR concepts is a plus. </span></li><li><span>Knowledge of PCB/interconnect structures (vias, connectors, transmission lines, stack-ups, materials) and manufacturing considerations. </span></li><li><span>Programming/scripting skills for automation and data analysis (Python preferred; MATLAB/C++ also acceptable). </span></li><li><span>Experience using lab instrumentation (oscilloscopes, signal generators/analyzers, power supplies, probes) and good measurement discipline.</span></li></ul><p></p><p> </p><p></p><p></p>A candidate who accepts an offer of employment in Mexico is required to present their own personal identification information and numbers for the following: Mexican Security Number (NSS), Tax Identification Number (RFC) and CURP identification number.<p style="text-align:inherit"> </p><h2>Job Type:</h2>Student / Intern<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Shift:</h2>Shift 1 (Mexico)<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Primary Location: </h2>Mexico, Guadalajara<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Additional Locations:</h2><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Business group:</h2>At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.<p style="text-align:inherit"></p><p style="text-align:inherit"></p><h2>Posting Statement:</h2>All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.<h2></h2><h2>Position of Trust</h2>N/A<p></p><p><b>Work Model for this Role</b></p>This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.<p></p><p>*</p><p></p>ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
