The Physical Design Engineer (EM/IR Closure Engineer) is a hands-on individual contributor responsible for block-level and subsystem-level EM/IR analysis and closure.
The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close collaboration with Physical Design, STA, and Methodology teams while operating within established SAM signoff frameworks.
We invite you to apply and be part of our mission to deliver world-class semiconductor solutions. Join us in shaping the future of technology.
Responsibilities will include but are not limited to:
- Execute physical design implementation from RTL to GDS, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution.
- Conduct verification and signoff, including formal equivalence verification, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and timing analysis.
- Identify and resolve violations, making recommendations for current and future product architectures.
- Optimize designs to enhance metrics such as power, frequency, and area using industry-standard EDA tools.
- Develop and improve physical design methodologies, automation flows, and processes.
- Possess expertise in structural and physical design, including timing closure, physical clock design, and multiple power domain analysis.
- Define and apply constraints for hierarchical design integration and floor planning concepts.
- Collaborate with cross-functional teams to ensure designs meet Intel's quality and performance standards.
The ideal candidate should show the following behavioral traits:
- Strong cross-team collaboration skills.
Minimum Qualifications are required to be initially considered for this position .
- Bachelor's or BS degree in Electronics Engineering, Computer Engineering, or related specialized field with 3+ years of experience.
- OR Master's degree in Electronics Engineering, Computer Engineering, or related specialized field with 2+ years of experience.
- OR PhD in Electronics Engineering, Computer Engineering, or related specialized field with no experience required.
- Experience listed above should be a combination of the following:
- Proficiency in scripting languages (e.g., Python, Tcl, Perl) for design flow automation.
- Expertise in static timing analysis, layout verification tools such as Calibre DRC, and physical clock design.
- Physical design implementation for custom IP and SoC designs using industry-standard tools such as Synopsys or Cadence.
- Intermediate to advanced English level.
Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).
Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Relevant Physical Design or Signoff experience.
- Working knowledge of Synopsys/Ansys signoff tools such as PrimeTime PX, PrimeRail, Redhawk etc.
- Understanding power delivery networks, reliability fundamentals, and signoff criteria.
- Experience working with Physical Design ECO cycles and closure loops.
- Scripting experience in TCL and/or Python.
- Hands-on experience with EM/IR analysis and closure for advanced nodes such as 3nm or below.
Requirements listed would be obtained through a combination of relevant industry job experience, internship experience, and/or schoolwork/classes/research.
Experienced Hire
Shift 1 (Mexico)
Mexico, Guadalajara
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
