20 publicaciones de empleo destacadas de lead principal engineer, layout en guadalajara, jal (¡Están contratando!)

Lead Principal Engineer, Layout Design
Micron —Tlaquepaque, Jal.
- Administración de personal
- Doctorado
- CAD
Senior Manager, Operating Unit Engineer
PACTIV FOODSERVICE MEXICO —Zapopan, Jal.
- $80,000 a $85,000 por mes
- Tiempo completo
- Bilingüe
- Español
- Ingeniería
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1d
Server Systems-Lead Engineer
FICO —Guadalajara, Jal.
- Tiempo completo
- Administración de personal
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Principal Engineering Services Engineer (Industrial Engineering)
Jabil Circuit —Guadalajara, Jal.
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Lead Staff Engineer, Layout Design
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Micron —Tlaquepaque, Jal.
- Doctorado
- Informática
- Diagramas
Senior Engineer Customer Applications
Infineon Technologies AG —Guadalajara, Jal.
- Inglés
- Maestría
- Licenciatura
Hardware Engineer
Bosch Group —Guadalajara, Jal.
- Tiempo completo
- Administración de personal
- CAD
- Ensamblaje
- Programa de referidos
Postulación rápida
Manager Design Review - Premium Brands
InterContinental Hotels Group —Guadalajara, Jal.
- Microsoft Word
- Administración de personal
- Inglés
New College Grad - HBM Layout Engineer
Micron —Tlaquepaque, Jal.
- Doctorado
- Inglés
- Maestría
Pathfinding Senior Design Layout Engineer
Micron —Tlaquepaque, Jal.
- Maestría
- Licenciatura
- Sin título de educación superior
Design Engineer
Eaton —Zapopan, Jal.
- Administración de personal
- CAD
- ERP systems
11d
Analog IC Layout Engineer
NXP Semiconductors —Guadalajara, Jal.
- Tiempo completo
- Inglés
- Licenciatura
- Mejora continua
14d
Gerente de Operaciones Metalmecánica
FRIMAX CARROCERIAS S DE RL DE CV —Tlaquepaque, Jal.
- $50,000 a $65,000 por mes
- Correo electrónico
- ERP systems
- Mejora continua
- Recursos humanos
- Oportunidades de crecimiento
- Seguro de vida
Postulación rápida
10d
Facilities Manager II
Jabil Circuit —Guadalajara, Jal.
- Tiempo completo
- Microsoft Powerpoint
- Microsoft Word
- Microsoft Excel
5d
Design Layout Engineer
Micron —Tlaquepaque, Jal.
- CAD
- Licenciatura
- Sin título de educación superior
Project Engineer III
Jabil Circuit —Guadalajara, Jal.
- Tiempo completo
- Microsoft Powerpoint
- Microsoft Word
- Microsoft Excel
7d
Ingeniero de procesos
PENSKE LOGISTICA —Zapopan, Jal.
- Tiempo completo
- Administración de personal
- Inglés
- Sin título de educación superior
- Vacaciones adicionales o permisos con goce de sueldo
- Seguro de vida
Postulación rápida
NCG Pathfinding Design Layout Engineer
Micron —Tlaquepaque, Jal.
- Maestría
- Licenciatura
- Capacitación
Production Supervisor
Flex LTD —Guadalajara, Jal.
- Tiempo completo
- Microsoft Excel
- ERP systems
- Mejora continua
- Seguro de vida

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Lead Principal Engineer, Layout Design

Micron -
Tlaquepaque, Jal.

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Información del empleo

Cualificaciones

Administración de personal
Node.js
Doctorado
CAD
Maestría
Licenciatura
Debugging

Descripción completa del empleo

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

As a Lead Principal Engineer, Layout Design at Micron, you will be at the forefront of developing groundbreaking memory solutions! This role is an outstanding opportunity to lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts. You will collaborate with a world-class team of Circuit Designers, Verification Engineers, CAD/Methodology experts, Process Integrators, Product Engineers, Test/Probe specialists, Assembly professionals, and Marketing strategists. Together, we will drive cost, quality, reliability, time-to-market, and customer happiness through outstanding layout and build.

Key Responsibilities

Lead the layout build and physical realization of new memory products.
Interpret device and circuit specifications to implement custom layout solutions meeting PPA (power, performance, area) and reliability targets.
Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools.
Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability.
Optimize layout for critical metrics such as die size/area efficiency, matching, coupling/noise, and timing.
Produce layout collateral and documentation for cross-team integration.

Physical Verification and Tapeout Signoff

Run and debug physical verification flows and ensure closure using industry tools.
Perform parasitic extraction and work with circuit designers to assess impact on timing, power, noise, and functionality.
Resolve layout issues related to signal integrity, coupling/crosstalk, antenna effects, and power integrity.

Technical Expertise and Training

Drive standard physical build practices and maintain layout documentation.
Participate in continuing education on advanced nodes and industry trends.
Solicit feedback from various groups to ensure layout quality and tool-flow robustness.
Innovate for future memory generations through layout-centric optimizations and improved methodologies.

Project Management

Lead resource planning, priorities, and tapeout schedules across multiple blocks.
Serve as the contact for layout implementation, physical verification, PEX/signoff, and integration issues.
Track closure of achievements and coordinate ECO execution to meet tapeout landmarks.
Communicate implementation status to technical leadership and management.

Minimum Qualifications

10+ years of experience in the Semiconductor industry.
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
Strong understanding of CMOS devices and layout-dependent effects.
Hands-on experience with custom IC layout and physical verification tools.
Comprehensive understanding of reliability checks and layout constraints.
Experience leading technical execution and delivering tapeouts.
Proficiency in scripting/automation to improve layout efficiency.

Preferred Qualifications

Master's Degree or PhD in Electrical/Computer Engineering or related field, or equivalent experience in lieu of either degree.
Excellent problem-solving and debug skills.
Self-motivated and diligent with the ability to prioritize multiple tasks.
In-depth knowledge of advanced-node layout considerations and memory/storage technology trends.
Strong communication skills to align constraints and tradeoffs.

Join Micron and be part of a team that's transforming the future of memory technology!

"The specified role does not encompass the following responsibilities: Finalization of sales agreements or the execution of sales contracts is prohibited. The role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination. Furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts. These activities fall beyond the permissible duties of the position."

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact [email protected]

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

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