QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
As a DTCO and Timing Engineer, you will play a vital role in DTCO analysis targeting the Mobile, Compute, Automotive and IOT markets
- The candidate will work with best-in-class methodologies, tools and implementation flows/technologies to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level in advanced process technologies 5nm, 4nm … 2nm and beyond (process technologies).
- Responsible for Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation and STA sign off using PT/PT-SI and Tempus.
- The candidate will be responsible for block level PPA analysis/implementation (RTL to GDS flow) for hard macros using FC Synthesis, FC Place and Route, Genus and Innovus,
- The candidate will be responsible for design implementation of multiple blocks working with foundry DTCO team , EDA companies (partners), CAD team and IP team driving Fmax optimization , PPAY and cost improvements/reduction.
- You should have good execution knowledge.
- Your contribution should improve design convergence process across the company, design PPAY and support new advanced process technologies bring-up in production from pdk to vlsi design.
- You should have good programming skills Python, Perl, TCL, Unix shell , C/C++.
- ML modeling experience is a plus
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
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